(1) Field of the Invention
The present invention relates to the field of digital arithmetic circuits and, more particularly, a binary digital arithmetic summarizer (Adder-Subtractor-Comparator) using digital logic circuits.
(2) Description of Related Art
Many computer related books state that a computer can perform only the following three basic functions: addition, subtraction and comparison. Most of today's computers perform arithmetic operations using adders, mostly implemented by digital logic functions (or circuits). Reference is made to the following exemplary U.S. Patent documents that disclose various arithmetic computing devices: 2006/0064455; 2004/0021482; 2003/0158882; 2003/0028575; 2002/0188641; 6,781,412; 6,505,226; 5,905,662; 4,970,677; 4,942,548; 4,897,808; 4,766,565; 4,685,079; 4,559,608; 4,254,471; 3,843,876; 3,679,883; 3,646,332; 3,602,705; 3,465,133; 3,482,085. Also many educational WEB sites contain and publish educational literature: www.shef.ac.uk/physics/teaching/phy107/logicsub.html is related to a subtractor circuit, and www.ece.umd.edu/˜ppetrov/ENEE244_FA06/Adders.ppt is related to a full adder circuit.
In addition to the fundamental arithmetical operation in digital electronics, all arithmetical computations (Adding and Subtracting) can be reduced to a simple addition operation. For example, subtraction can be treated as addition by the use of complementary numbers. FIG. 1A illustrates a well-known, conventional 1-bit full adder 100 that has been in use for many years, and FIG. 1B illustrates a corresponding truth table for the 1-bit full adder of FIG. 1A.
As illustrated in FIG. 1A, conventional 1-bit full adders are comprised of an XOR function logic gate 102 that receives input values from the A and B registers, which contain or hold two numbers or operands on which the addition operation of the full adder 100 will operate. The A and B registers are further coupled to an AND function logic gate 106. With the combination of the XOR function logic gate 102 and the AND function logic gate 106 forming the first half of the full adder. Further included with the full adder 100 of FIG. 1A are a second XOR function logic gate 104, a second AND function logic gate 108, and an OR function logic gate 110, which combine the “Carry” signals form the current bit and from the previous bit's operation, forming the full adder circuit 100.
The function of the first AND logic gate 106 is to create the “Carry” signal if both of the input operands has a high (=1) input value. The function of the second AND logic gate 108 is to create the “Carry” signal if only one of the input operands and the Carry from the previous adjacent lower Bit's operation has a high (=1) input value. The operation of the 1-bit full adder circuit 100 is best explained by the use of the truth table as illustrated in FIG. 1B. In the selected case (112), register A contains or holds the logic value of “1” and the register B contains the logic value of “1”, and the carry-in register Ci holds the logic value “0”. The output signals are the combined results of the logic functions gates 106, 108, 110 and 104 as illustrated in the selected case (112), as the Sum bit output holds a low value (=0) and the Carry bit output holds a high value (=1). Since this full Adder circuit is well-known and it has been in use for many years, no further explanation is required.
FIG. 1C illustrates an implementation of the well-known, 1-bit subtractor 120 that has been in use for many years, and FIG. 1D illustrates a corresponding truth table for the 1-bit full subtractor of FIG. 1C. As illustrated in FIG. 1C, this 1-bit full subtractor is similar to the 1-bit full adders, with the exception that the value of register A (the minuend operand) is inverted by the INV function logic gate 126 prior to its application to the AND function logic gate 122. In addition, the output of the first XOR function logic gate 102 is first inverted by the INV function logic gate 128 prior to input to the AND function logic gate 124. The inversion operation of the INV function logic gate 128 provides the actual complimentary values needed for performing subtraction. Therefore, this prior art device is based on and uses the concept of “borrowing” to execute the actual subtraction operations on two operands, using binary complement operations on the subtrahend. The selected case of the FIG. 1D truth table (132) illustrates the input operands, the Borrow in, the Borrow out and the Difference bits values.
It should be noted, this prior art subtractor circuit 120 requires seven (7) logic function gates to complete one functional unit.
As stated above, in prior art electronics and computer arithmetic the subtraction operation can be treated as addition by the use of complementary numbers. The procedure for subtraction with either 1's or 2's complement is well known, and described in numerous publications. Referring to FIG. 1E, the A register holds the value for an exemplary three bit binary operand “011” as the minuend in the subtraction operation and the B register holds the value for an operand “101” as the subtrahend. The subtraction of these two binary numbers should be done by taking the complement of the subtrahend (content of the B register) and adding it to the minuend (content of the A register). In FIG. 1E the subtrahend (B register) has a larger value than the minuend (A register). This well-known procedure is systematically illustrated in FIG. 1E, with no further explanation. FIG. 1F is the other example for binary subtraction. In FIG. 1F, the A-Register holds the value for an exemplary three-bit binary operand “101” as the minuend in the subtraction operation, and B register holds the value for an operand “011” as the subtrahend. In FIG. 1F the subtrahend (B register) has a smaller value than the minuend (A register). This is also a well-known procedure and is systematically illustrated in FIG. 1F, without further explanations. It should be noted that both exemplary subtractions include multiple additions.
In “real world” applications for execution of subtraction operations, most prior art circuits use 1's or 2's complements, and perform multiple addition iterations before obtaining the final result. The subtractor circuit (120) illustrated in FIG. 1C requires multiple secondary operations if the subtrahend operand has a higher value than the minuend operand. Further, subtraction operations performed by most prior art circuits require the use of temporary storage devices such as a flip-flop to keep track of the iterating results. In order to avoid the use of complementary operations when executing subtraction operations, some prior art circuits swap the contents of the operands of two registers. That is, the operand with a larger magnitude in a second register is swapped with the operand with a smaller magnitude in a first register. This assures that the “subtrahend” register always contains an operand with smaller magnitude than the operand within the “minuend” register, thereby avoiding the use of one extra addition operation. However, the swapping operation between the operands of two registers is time consuming, which further slows the subtraction operation.
Accordingly, in light of the current state of the art and the drawbacks to computing devices mentioned above, a need exists for a computing device as described in the followings.